Dielectric breakdown of internal input and output MOS transistor elements is a significant factor in the failure of MOS IC devices. An input 10 for such a device is illustrated in the fragmentary circuit diagram of FIG. 1 where the gate G of an internal input NMOS transistor element is connected by a metal conductor to the bond pad 12 for coupling to external circuitry. The gate G of the NMOS transistor element is insulated from the drain D, channel C and source S regions of the NMOS transistor element by a thin gate oxide (GOX) layer 14 of thermally grown silicon dioxide SiO.sub.2. The channel C between drain D and source S merges with the P Well or bulk B of the NMOS transistor element which is typically coupled with source S to ground potential GND. The thin GOX layer 14 is typically grown to a depth or thickness of for example 225 .ANG.-400 .ANG. (angstrom units). The thin GOX layer 14 can withstand a voltage stress across the gate G and channel C of only up to for example approximately 15 volts without dielectric breakdown and failure of the transistor element and MOS IC device.
During handling of the MOS IC device, the bond pad 12 coupled to the outside world may receive electrostatic discharges (ESD) causing positive and negative transient voltage spikes 15, 16 on the input conductor. The charge buildup on the bond pad and transient voltage spikes, which may be as great, for example, as 10,000 volts, are fed to the gate G of internal MOSFET's including the illustrated NMOS transistor element and other PMOS and NMOS transistor elements coupled to the input line 18.
It is apparent that in order to prevent failure, ESD voltage spikes greater than or equal to the gate oxide layer breakdown voltage BVGOX of approximately 15 volts must be avoided, or diverted, or cancelled. Generally, a voltage greater than 10 to 15 volts across the GOX layer 14 should always be prevented. An early solution for preventing ESD spike voltages greater than 15 volts from reaching the MOSFET gates was to divert the voltage spikes through spark gap discharge to pointed metal discharge paths positioned along the input line and coupled to ground. The pointed aluminum metal discharge paths provide graduated spark gap discharge voltage breakdown paths less than the dielectric breakdown voltage BVGOX of the internal transistor gate oxide layers. This expedient is no longer permitted because of the electromagnetic interference (EMI) and radio frequency interference (RFI) caused by pointed metal spark gap discharge.
ESD protection is currently provided by clamping the input or output line using ESDP diodes as illustrated in the input circuit 20 of FIG. 2. The ESDP diodes D1 and D2 are arranged to prevent over stress of GOX layers 14 from electrostatic charge voltages. Positive voltage spikes instead of building up voltage across the MOSFET gate and channel, discharge to the high potential voltage source V.sub.cc through the conduction path provided by clamping diode D1. ESDP diode D1 is typically a P.sup.+ to N.sup.- junction. For example an ESD voltage spike of +15 v causes current flow in the direction from cathode to anode of diode D1 to the lower +5 voltage source V.sub.cc. Negative voltage spikes for example of -15 v to -20 v cause current to flow from ground in the cathode to anode direction of diode D2 cancelling the voltage buildup. In each example electron flow is in the opposite direction to current flow.
As shown in FIG. 2 a current limiting resistor R1 may be added in series with the ESDP diodes D1 and D2 to slow down charge buildup. A disadvantage of the conventional arrangement of FIG. 2 is that the current limiting resistor R1 in combination with the capacitor junctions of the diode elements D1 and D2 results in an RC time constant delay in biasing the diodes to start conducting and diverting or cancelling electrostatic charge buildup. Since the duration of the transient ESD may be in nanoseconds, the dielectric breakdown voltage BVGOX at the input MOS transistor gates may be exceeded before the conducting paths through diodes D1 and D2 are fully established.
Another disadvantage of the conventional diode clamping ESDP arrangement of FIG. 2 occurs during "power down" applications of the MOS IC device. In power down applications, the voltage source V.sub.cc node is reduced from 5 volts to 0 volts to conserve energy, reduce heat, etc. Power down is typically used in battery powered applications such as lap top computers and modular systems with separately controlled modules on the mother board. While ESDP diode clamp D1 may provide satisfactory operation with the V.sub.cc node at 5 v, a problem is encountered with the V.sub.cc node at 0 v while the data circuit input remains connected with the power off.
The P.sup.+ /N.sup.- junction of the clamping diode D1 provides a direct path to the silicon substrate of a P well MOS IC device for positive voltages appearing at the input bond pad. Each time the input goes high from a data signal coupled to the input, a charge is pumped into the substrate which acts as a large capacitance for storage of the positive charge. This phenomenon of input "wiggling" eventually builds up sufficient voltage in the substrate to act as a positive power supply battery powering up the MOS IC device and turning it back on.
A possible solution to the problem of "wiggling" encountered in power down applications, is to remove the V.sub.cc conduction path diode D1 and accompanying P+/N- path to substrate. However, removal of diode D1 leaves no protection against positive going ESD voltage spikes. A further expedient is therefore required for diverting, dissipating and protecting against positive electrostatic discharge. It would be desirable that any added ESD protection without the P+/N- V.sub.cc diode be incorporated in the MOS IC device without added steps during the fabrication process.
The process for fabrication of the internal transistor elements of the MOS IC device is illustrated in FIGS. 3-7. The wafer fabrication process generally follows the following mask sequence and associated mask steps.
0 P Well Definition Mask PA1 1.0 Active Area Definition Mask PA1 2.0 P Well Field Implant Mask PA1 3.0 Poly Definition Mask (Gate Definition Mask For Internal Transistors) PA1 4.0 N.sup.+ Source/Drain Implant Mask (Self-Aligned Internal NMOS Transistor Mask) PA1 4.1 P.sup.+ Source/Drain Implant Mask (Self-Aligned Internal PMOS Transistor Mask) PA1 5.0 Contact Definition Mask PA1 6.0 Metal 1 (M1) Definition Mask PA1 7.0 VIA Mask (Second Contact Definition Mask) PA1 8.0 Metal 2 (M2) Definition Mask PA1 9.0 Passivation Definition Mask
As illustrated in FIG. 3 the fabrication process begins with a substrate of N.sup.+ silicon semiconductor material prepared with an N.sup.- silicon epitaxial layer and thin protective layers of thermally grown silicon dioxide SiO.sub.2 and silicon nitride Si.sub.3 N.sub.4. The oxide layer is typically 400 .ANG. and the nitride layer 1600 .ANG.. A photoresist layer is "spun on" and patterned to provide the 0 Mask or P Well Definition Mask defining the P.sup.- wells for NMOS transistor elements. The nitride layer is stripped in a dry etch over the P.sup.- well area and P.sup.- wells are established by a P.sup.- boron ion implant. As used herein the plus and minus superscripts indicate the relative concentration of N type or P type dopant material in the silicon semiconductor material and the relative conductivity of the silicon regions.
In subsequent steps the P.sup.- implant ions are thermally driven into the P.sup.- well and a relatively thick oxide layer is thermally grown over the P.sup.- well to act as a barrier to the subsequent N.sup.- implant. The remaining portions of the nitride layer are stripped in a wet etch. An N.sup.- implant of N type dopant material ions such as phosphorus ions establishes the N.sup.- wells for PMOS transistor elements outside the P.sup.- well areas as shown in FIG. 4.
The silicon dioxide layer grown over the P.sup.- well is stripped in a wet etch and a new thin oxide layer is grown to a depth of 400 .ANG. across the chip. An N well drive step drives the implanted N type phosphorus dopant material deeper into the N.sup.- wells and enhances the epitaxial layer.
A new nitride layer is deposited to a thickness of 1600 .ANG. across the chip and the nitride layer is patterned and etched using the photoresist 1.0 Active Area Definition Mask, not illustrated. The active area definition mask and etch step leaves islands of silicon nitride over the P.sup.- wells and N.sup.- wells coinciding with the active areas for NMOS and PMOS transistor elements respectively. The wells are thus wider or larger in area than the active areas of the respective transistor elements which are limited to the areas of the silicon nitride islands illustrated in FIG. 5. The 1.0 Mask and resulting nitride island define the channel width of the NMOS & PMOS transistor elements.
The photoresist 2.0 P Well Field Implant Mask is next formed covering the N.sup.- wells followed by the P.sup.+ field implants. The 2.0 P Well Field Implant Mask, also referred to as the N Channel Field Implant Mask, is similar to the 0 P Well Definition Mask but leaves openings slightly larger for example 2.mu. outside the original P.sup.- well areas. The P.sup.+ field implant establishes P.sup.+ channel stop regions to increase the threshold voltage or turn on voltage V.sub.TON of parasitic transistor structures that arise between active areas across the field oxide hereafter described. The P.sup.+ field implant is a boron ion implant on all sides of the nitride island rectangle coinciding with the active area of the NMOS transistor elements to be fabricated in the P.sup.- wells.
Following the P.sup.+ field implant and stripping of the 2.0 Mask the field oxide regions are grown between the nitride islands, surrounding the nitride islands for isolating the active areas. The field oxide or FOX is grown to a thickness of, for example, 6000 .ANG.. The nitride islands prevent growth of FOX in the active areas of the NMOS and PMOS transistor elements. The nitride islands are then stripped from the chip. A blanket boron implant is used to adjust the carrier concentration and turn on voltage V.sub.TON of the active areas, and then the thin oxide layer is removed.
A thin gate oxide layer GOX of approximately 225 .ANG. is grown over the active areas. A blanket layer of polycrystalline silicon (poly) is then deposited to a depth of for example 3500 .ANG. across the chip and the surface of the poly layer is oxidized to form a thin protective polyoxide layer.
The poly layer is then patterned using the 3.0 Poly Definition Mask, not illustrated, and the poly definition mask and etch steps leave gates of polysilicon over the active areas as illustrated in FIG. 6. In FIG. 6, a poly gate is shown over the P.sup.- well for an NMOS transistor element and over the N.sup.- well for a PMOS transistor element. The poly gates are smaller than the active areas of the respective transistor elements and define the channel length of the respective transistor elements. The photoresist 3.0 Poly Definition Mask also functions as the gate definition mask for internal transistor elements.
The poly gates for the NMOS transistor elements over the P.sup.- wells in combination with the photoresist 4.0 N.sup.+ Source/Drain Implant Mask provide a self-aligned transistor mask for the internal NMOS transistor elements. An N.sup.+ implant follows establishing the N.sup.+ drain and source regions for the NMOS transistor elements as illustrated in FIG. 6. The photoresist 4.0 Mask opens a small area over the N.sup.- well also for an N.sup.+ substrate tie N.sup.+ ST for N.sup.- well substrate ties.
The photoresist 4.1 P.sup.+ Source/Drain Implant Mask not illustrated is similar to the 4.0 mask of FIG. 6 but covers the P.sup.- wells and active areas for the NMOS transistor elements. The N.sup.- wells and active areas of the PMOS transistor elements are exposed for P.sup.+ implant of the P.sup.+ source and drain regions of the PMOS transistor elements. Similarly a small opening is provided over the P.sup.- well to establish P.sup.+ substrate ties P.sup.+ ST for P.sup.- well substrate ties. In effect the 4.1 Mask and associated 4.1 Mask steps are the inverse of the 4.0 Mask and associated 4.0 Mask steps.
The 4.0 Mask N.sup.+ implant of N type dopant material ions may be accomplished in two steps, first implanting heavier arsenic ions followed by implanting lighter phosphorus ions which diffuse faster and deepen the N.sup.+ region. A graded concentration profile can therefore be established. Upon completion of implant of the source and drain regions, the photoresist 4.0 and 4.1 Masks are stripped and a blanket passivating layer of for example, low temperature semiconductor material oxide (LTO) is deposited to a depth typically in the range of 5000 .ANG. to 6500 .ANG.. The LTO or other passivating material may be deposited by chemical vapor deposition to a depth of, for example, 6.3K .ANG.. The blanket passivating layer is patterned and etched using the photoresist 5.0 Contact Definition Mask, not illustrated, for defining and establishing the openings in the LTO or other passivating material layer for metal contacts from the Metal 1 layer hereafter described.
For the internal transistor elements, the LTO layer provides an insulating passivating layer over the poly gate and between the poly gate and M1 layer as illustrated in FIG. 7. The 5.0 Contact Definition Mask defines the metal conductor contacts to the source and drain regions. The first metal layer is deposited over the patterned passivating layer and the Metal 1 layer is masked and etched using the 6.0 M1 Definition Mask leaving the source and drain metal contacts and conductors. The M1 layer also provides the first layer for bond pads of the MOS IC device.
A second LTO layer or other interlayer dielectric (ILD) material layer is deposited, masked and etched using the 7.0 VIA Mask which defines openings for contacts between the Metal 2 layer and Metal 1 layer including the openings for bond pads. The 7.0 VIA Mask is a second contact definition mask for the second LTO or ILD layer. The second metal layer is deposited, masked and etched using the photoresist 8.0 M2 Definition Mask. The second metal layer M2 in parallel with the first metal layer M1 reduces current density etc. It also provides the second metal layer for the bond pads. The bond pads are formed of composite or merged portions of layers M1 and M2. The final steps include depositing a passivating nitride layer over, the entire chip followed by the photoresist 9.0 Passivation Definition Mask and etch steps for opening the bond pads.